A processor includes a set of microcode routines that lie dormant until activated by a software write to a control register (e.g., Write to Model Specific Register (WRMSR) instruction). The set of microcode routines is referred to herein as “tracer,” which is used as a tool to debug and performance tune the processor. Once activated, various events can trigger the tracer to gather processor state information and write it to specified addresses in memory so that it can be captured by a logic analyzer monitoring the external processor bus. The state information can include the contents of the register sets; translation-lookaside buffers; cache memories, such as data caches, instruction caches, branch target address caches, level-2 caches; a private random access memory (RAM) (described in U.S. patent application Ser. No. 12/034,503, filed Feb. 20, 2008, which claims priority to U.S. Provisional Application 60/910,982, filed Apr. 10, 2007, each of which is hereby incorporated by reference in its entirety for all purposes) of the processor 102; and so forth. The state information and other information associated with it (e.g., time information) is referred to herein as log information, or simply a log. The events can also trigger tracer to perform other actions, such as clearing various state (e.g., write-back invalidate caches, clear translation lookaside buffers (TLBs), least-recently-used (LRU) arrays, branch prediction information), or causing the processor to take an system management interrupt (SMI) to a private system management mode (SMM) address allocated for tracer. Event examples include: execution of a specified instruction, such as RDTSC, RDPMC, XSTORE (store random numbers), MOV to CR (control register), WRMSR, RDMSR, software interrupt instructions, SYSENTER/SYSEXIT/SYSCALL/SYSRET, CPUID, RSM, MWAIT, MONITOR, VMLAUNCH, VMRESUME, IRET, IN, OUT); an x86 exception; interrupts, such as SMI, INTR, NMI, STPCLK, A20; virtual machine (VM) exit condition; machine check; and read/write an Advanced Programmable Interrupt Controller (APIC) register.
Tracer is a very powerful tool; however, it has two main limitations. First, tracer is implemented as microcode instructions within the processor; consequently, by executing tracer, the state of the processor changes from what the processor state would be without tracer having been activated and triggered. That is, tracer may be disruptive to the normal processor state that is created by the program being debugged or tuned, which may reduce tracer's usefulness. For example, tracer may make the bug go away or may affect the performance of the processor. Second, because tracer is a set of microcode routines, the tracer routines can only run when the processor is executing microcode-implemented instructions or if a hardware interrupt causes the processor to go to microcode; however, there are events that are important to debugging or tuning that can occur asynchronously to the execution of instructions, i.e., during the midst of the execution of an instruction, some of which may take many clock cycles to execute, during which the tracer microcode does not get to run. For example, the processor voltage or bus clock ratio may change at any time regardless of which instructions the processor is currently executing and may occur at any time during the execution of an instruction or set of instructions.